Semiconductor device and manufacturing method thereof

ABSTRACT

An object is to obtain a semiconductor device in which channel length is reduced without increasing the gate resistance to realize higher operation speed and its manufacturing method. An MOSFET has a trench-type element isolation structure ( 2 ) formed in the main surface of a semiconductor substrate ( 1 ), a pair of extensions ( 3 ) and source/drain regions ( 4 ) selectively formed in the main surface of the semiconductor substrate ( 1 ) to face each other through a channel region ( 50 ), a silicon oxide film ( 5 ) formed on the trench-type element isolation structure ( 2 ) and on the source/drain regions ( 4 ) through a silicon oxide film ( 12 ), sidewalls ( 6 ) formed on sides of the silicon oxide film ( 5 ), a gate insulating film ( 7 ) formed on the main surface of the semiconductor substrate ( 1 ) in the part in which the channel region ( 50 ) is formed, and a gate electrode ( 8 ) formed to fill a recessed portion in an inversely tapered form formed by the sides of the sidewalls ( 6 ) and the upper surface of the gate insulating film ( 7 ).

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to semiconductor devices andmanufacturing methods thereof, and particularly to an MOSFET having agate electrode formed of metal film and a manufacturing method thereof.

[0003] 2. Description of the Background Art

[0004] Polycide gates having stacked structure of polysilicon film andmetal silicide film are widely used as the gate electrodes of MOSFETs.However, formation of the gate electrodes with metal film, such astungsten film, is effective to reduce the gate resistance so as torealize higher-speed operation of the MOSFETs.

[0005] When a gate electrode is formed of metal film, heat treatmentafter the formation of the gate electrode is restricted because of thelow thermal resistance of the metal film and some other reasons. Forexample, the heat treatment to the source/drain regions which areusually formed after the formation of the gate electrode is restrictedand the dopant is insufficiently activated, and then the source/drainresistance is increased to lower the driving capability of the MOSFET.To solve this inconvenience, a method of forming the source/drainregions before formation of the gate electrode is suggested, in which adummy electrode is formed for the gate electrode (the replace method).

[0006]FIG. 36 is a sectional view showing the structure of an MOSFEThaving a gate electrode formed by a conventional replace method (Ext.Abst. of International Electron Devices Meeting 1998, pp.785-788). Theconventional MOSFET shown in FIG. 36 has a semiconductor substrate 101,a trench-type element isolation structure 102 formed in the elementisolation region in the main surface of the semiconductor substrate 101,a pair of source/drain regions 103, selectively formed in the elementformation region in the main surface of the semiconductor substrate 101to face each other through the channel region, a silicon oxide film 104formed on the trench-type element isolation structure 102 and on thesource/drain regions 103 through a silicon oxide film 108, a gateinsulating film 105 formed on the main surface of the semiconductorsubstrate 101 in the part in which the silicon oxide film 104 is notformed in the element formation region, and a gate electrode 106 formedto fill the recessed portion formed by sides of the silicon oxide film104 and the upper surface of the gate insulating film 105.

[0007] FIGS. 37 to 42 are sectional views showing a method formanufacturing the MOSFET shown in FIG. 36 in the order of process steps.First, the trench-type element isolation structure 102 filled withinsulating film is formed in the element isolation region in the mainsurface of the semiconductor substrate 101 which is composed of singlecrystal silicon. Next, to form a well and to adjust the operationthreshold voltage of the MOSFET, boron ions 107 are implanted into thesemiconductor substrate 101 by an ion implantation (FIG. 37).

[0008] Next, the silicon oxide film 108 is formed by a thermal oxidationon the main surface of the semiconductor substrate 101. Subsequently, apolysilicon film and a silicon nitride film are formed in this order byCVD on the silicon oxide film 108. After this, the polysilicon film andthe silicon nitride film are patterned into given shape byphotolithography and anisotropic dry etching to selectively form a dummyelectrode 150 on the silicon oxide film 108; the dummy electrode 150 hasa stacked structure in which the polysilicon film 109 and the siliconnitride film 110 are stacked in this order (FIG. 38).

[0009] Next, arsenic ions 111 are implanted into the semiconductorsubstrate 101 by an ion implantation to form the source/drain regions103 in the main surface of the semiconductor substrate 101 (FIG. 39).Subsequently, a thermal treatment is performed to activate the implantedarsenic ions 111. Next, a silicon oxide film is formed on the entiresurface by a CVD. After that, the silicon oxide film is polished by CMP(Chemical Mechanical Polishing) until the upper surface of the dummyelectrode 150 is exposed to form the silicon oxide film 104 (FIG. 40).Next, the dummy electrode 150 and the silicon oxide film 108 under thedummy electrode 150 are removed (FIG. 41). In FIG. 41, the silicon oxidefilms 104 and 108 serve as a mold for forming the gate electrode.

[0010] Next, the gate insulating film 105 composed of silicon oxide filmis formed on the main surface of the semiconductor substrate 101 by athermal oxidation. Subsequently, a tungsten film 113 is formed all overthe surface by CVD or sputtering (FIG. 42). Next, by the CMP method, thetungsten film 113 is polished until the upper surface of the siliconoxide film 104 is exposed, thus providing the structure shown in FIG.36.

[0011]FIG. 43 is a sectional view showing the structure of anotherMOSFET having a gate electrode formed by a conventional replace method.(Ext. Abst. of International Electron Devices Meeting 1998, pp.777-780).The conventional MOSFET shown in FIG. 43 has the semiconductor substrate101 and the trench-type element isolation structure 102 which are thesame as those in the MOSFET shown in FIG. 36, a pair of extensions 121and source/drain regions 122 selectively formed in the element formationregion in the main surface of the semiconductor substrate 101 to faceeach other with the channel region therebetween, a silicon oxide film123 formed on the trench-type element isolation structure 102 and on theextensions 121 with asilicon oxide film 127 interposed therebetween,sidewalls 124 formed in sides of the silicon oxide film 123, a gateinsulating film 125 formed on the main surface of the semiconductorsubstrate 101 in the part in which the silicon oxide film 123 and thesidewalls 124 are not formed in the element formation region, and a gateelectrode 126 formed to fill the recessed part formed by the sides ofthe sidewalls 124 and the upper surface of the gate insulating film 125.

[0012] FIGS. 44 to 50 are sectional views showing a method ofmanufacturing the MOSFET shown in FIG. 43 in the order of processes.First, by the same method as that described above, the same structure asthat shown in FIG. 37 is obtained. Subsequently, the silicon oxide film127 is formed on the main surface of the semiconductor substrate 101 bya thermal oxidation. Next, by CVD, a polysilicon film is formed on thesilicon oxide film 127. Then, the polysilicon film is patterned intogiven shape by photolithography and anisotropic dry etching toselectively form a dummy electrode 128 composed of polysilicon film onthe silicon oxide film 127 (FIG. 44).

[0013] Next, arsenic ions 129 are implanted by an ion implantation intothe semiconductor substrate 101 to form the extensions 121 in the mainsurface of the semiconductor substrate 101 (FIG. 45). Next, a siliconnitride film is formed on the entire surface by a CVD. Subsequently, thesilicon nitride film is etched by an anisotropic dry etching to form thesidewalls 124 composed of the silicon nitride film on the sides of thedummy electrode 128. After that, arsenic ions 130 are implanted into thesemiconductor substrate 101 by an ion implantation to form thesource/drain regions 122 which are deeper than the extensions 121 (FIG.46). Then a thermal treatment is applied to activate the implantedarsenic ions 130.

[0014] Next, a silicon oxide film is formed all over the surface by aCVD. Next, the silicon oxide film is polished by CMP until the uppersurface of the dummy electrode 128 is exposed to form the silicon oxidefilm 123 (FIG. 47). Next, the dummy electrode 128 and the silicon oxidefilm 127 under the dummy electrode 128 are removed (FIG. 48). In FIG.48, the silicon oxide films 123 and 127 and the sidewalls 124 serve as amold for forming the gate electrode.

[0015] Next, the gate insulating film 125 composed of silicon oxide filmis formed on the main surface of the semiconductor substrate 101 by athermal oxidation. After that, a tungsten nitride film 131 and atungsten film 132 are formed in this order by CVD or sputtering on theentire surface (FIG. 49). Next, by photolithography, a photoresist 133having a given pattern is formed on the tungsten film 132. After this,the tungsten nitride film 131 and the tungsten film 132 are etched by ananisotropic dry etching to form the gate electrode 126 made of thetungsten nitride film 134 and the tungsten film 135 (FIG. 50). As shownin FIG. 50, the side ends of the gate electrode 126 extend on thesilicon oxide film 123. Next, the photoresist 133 on the tungstennitride film 135 is removed to obtain the structure shown in FIG. 43.

[0016] These conventional semiconductor devices and manufacturingmethods have the following problems. First, while reducing the channellength is effective to enhance the driving capability of the MOSFET soas to increase the operating speed, the channel length in theconventional semiconductor device and manufacturing method shown inFIGS. 36 and 43, for example, is approximately equal to the gate lengthof the dummy electrode 150. Accordingly, since the channel length isdefined by the minimum resolution limit in the photolithographytechnique adopted when forming the dummy electrode 150, it is difficultto reduce the channel length. Furthermore, if the dummy electrode issimply downsized to reduce the channel length, it will raise the problemthat the gate resistance of the gate electrode increases.

[0017] Moreover, as shown in FIG. 36, for example, the upper surface ofthe gate electrode 106 composed of metal film is exposed in theconventional semiconductor device and its manufacturing method. Hence,when forming a contact hole to make electrical contact with thesource/drain regions, the self-aligned contact formation techniquecannot be used to avoid contact between the gate electrode and thecontact hole.

SUMMARY OF THE INVENTION

[0018] According to a first aspect of the present invention, asemiconductor device comprises: a substrate; source/drain regions formedin a main surface of the substrate with a channel region interposedtherebetween; a gate insulating film formed on the main surface of thesubstrate in an area in which the channel region is formed; and aninversely tapered gate electrode formed on an upper surface of the gateinsulating film.

[0019] According to a second aspect of the present invention, asemiconductor device comprises: a substrate; source/drain regions formedin a main surface of the substrate with a channel region interposedtherebetween; a first insulating film formed on the main surface of thesubstrate in an area in which the source/drain regions are formed;sidewalls composed of a second insulating film and formed on sides ofthe first insulating film; a gate insulating film composed of a thirdinsulating film and formed on the main surface of the substrate in anarea in which the channel region is formed; and a gate electrode formedto fill an inversely tapered recessed portion formed by sides of thesidewalls and an upper surface of the gate insulating film.

[0020] Preferably, according to a third aspect of the invention, in thesemiconductor device, the third insulating film is composed of amaterial having a larger dielectric constant than silicon oxide film.

[0021] Preferably, according to a fourth aspect of the invention, in thesemiconductor device, the third insulating film is formed to extend onlyonto the sides of the sidewalls.

[0022] Preferably, according to a fifth aspect of the invention, thesemiconductor device further comprises an impurity region locally formedin the substrate only under the gate insulating film and having aconductivity type which is opposite to that of the source/drain regions.

[0023] Preferably, according to a sixth aspect of the invention, in thesemiconductor device, the source/drain regions are formed in the mainsurface of the substrate also in areas in which the sidewalls areformed, and the semiconductor device further comprises an impurityregion locally formed in the substrate only under the gate insulatingfilm and the sidewalls and having a conductivity type which is oppositeto that of the source/drain regions.

[0024] Preferably, according to a seventh aspect of the invention, thesemiconductor device further comprises a fourth insulating film formedon an upper surface of the gate electrode and surrounding the gateelectrode with the sidewalls, wherein the second and fourth insulatingfilms are composed of a material which is different from that of thefirst insulating film.

[0025] Preferably, according to an eighth aspect of the invention, inthe semiconductor device, the gate electrode has its peripheral partformed to extend on an upper surface of the first insulating film.

[0026] According to a ninth aspect of the present invention, a methodfor manufacturing a semiconductor device comprises the steps of: (a)forming a structure on a main surface of a substrate in an area in whicha gate electrode is formed later; (b) forming source/drain regions inthe main surface of the substrate in an area in which the structure isnot formed; (c) forming a first insulating film on the main surface ofthe substrate in an area in which the structure is not formed; (d) afterthe step (c), removing the structure; (e) forming a second insulatingfilm on the construction obtained by the step (d) and etching the secondinsulating film by an anisotropic etching whose etching rate is higherin depth direction of the substrate to form sidewalls on sides of thefirst insulating film; (f) forming a gate insulating film composed of athird insulating film on the main surface of the substrate in an area inwhich the first insulting film and the sidewalls are not formed; and (g)forming the gate electrode to fill an inversely tapered recessed partformed by sides of the sidewalls and an upper surface of the gateinsulating film.

[0027] Preferably, according to a tenth aspect of the invention, in thesemiconductor device manufacturing method, in the step (a), thestructure is formed by stacking a first film composed of a materialwhich is different from that of the second insulating film and a secondfilm composed of a material which is different from that of the firstinsulating film in this order, and the step (d) comprises the steps of;(d-1) between the step (c) and the step (e), removing the second filmwith the first film left unremoved, and (d-2) between the step (e) andthe step (f), removing the first film by a wet etching.

[0028] Preferably, according to an eleventh aspect of the invention, inthe semiconductor device manufacturing method, in the step (a), thestructure is formed with a material which is different from that of thefirst insulating film, and in the step (d), the structure is removed bya wet etching.

[0029] Preferably, according to a twelfth aspect of the invention, inthe semiconductor device manufacturing method, in the step (f), thethird insulating film is formed with a material having a largerdielectric constant than silicon oxide film.

[0030] Preferably, according to a thirteenth aspect of the invention, inthe semiconductor device manufacturing method, the step (f) comprisesthe steps of; (x-1) forming the third insulating film on theconstruction obtained by the step (e), and (x-2) removing the thirdinsulating film formed on an upper surface of the first insulating film.

[0031] Preferably, according to a fourteenth aspect of the invention, inthe semiconductor device manufacturing method, the step (g) comprisesthe steps of; (y-1) after the step (x-1), forming a conductor film whichis a material of the gate electrode on the third insulating film, and(y-2) after the step (y-1), thinning the conductor film until the uppersurface of the first insulating film is exposed to form the gateinsulating film, and the step (x-2) is performed together in the processin which the step (y-2) is performed.

[0032] Preferably, according to a fifteenth aspect of the invention, inthe semiconductor device manufacturing method, the step (g) comprisesthe steps of; (z-1) after the step (x-1), forming a conductor film whichis a material of the gate electrode on the third insulating film, and(z-2) between the step (z-1) and the step (x-2), thinning the conductorfilm until the third insulating film formed on the upper surface of thefirst insulating film is exposed to form the gate electrode, and in thestep (x-2), the third insulating film is removed by etching the thirdinsulating film exposed in the step (z-2).

[0033] Preferably, according to a sixteenth aspect of the invention, thesemiconductor device manufacturing method further comprises the step of:(h) between the step (e) and the step (f), introducing an impurity intothe substrate by using the first insulating film and the sidewalls asmasks to form an impurity region having a conductivity type which isopposite to that of the source/drain regions.

[0034] Preferably, according to a seventeenth aspect of the invention,in the semiconductor device manufacturing method, in the step (b), thesource/drain regions are formed to extend also under peripheral part ofthe structure in the main surface of the substrate, and themanufacturing method further comprises the step of: (i) between the step(d) and the step (e), introducing an impurity into the substrate byusing the first insulating film as a mask to form an impurity regionhaving a conductivity type which is opposite to that of the source/drainregions.

[0035] Preferably, according to an eighteenth aspect of the invention,in the semiconductor device manufacturing method, the first insulatingfilm is composed of a material which is different from that of thesecond insulating film, and the manufacturing method further comprisesthe steps of; (j) removing the gate electrode for a given film thicknessfrom its upper surface, and (k) after the step (j), forming a fourthinsulating film composed of a material which is different from that ofthe first insulating film on the gate electrode.

[0036] Preferably, according to a nineteenth aspect of the invention, inthe semiconductor device manufacturing method, the step (g) comprisesthe steps of; (g-1) forming a conductor film which is a material of thegate electrode on the construction obtained by the step (f), and (g-2)patterning the conductor film to form the gate electrode having itsperipheral part extending on an upper surface of the first insulatingfilm.

[0037] According to the first aspect of the present invention, the gatelength in the upper part of the gate electrode is longer than that inits lower part, so that the gate resistance can be reduced withoutenlarging the channel length.

[0038] According to the second aspect of the invention, reflecting theshape of the sidewalls, the gate length in the upper part of the gateelectrode is longer than that in its lower part. Hence the gateresistance can be reduced without enlarging the channel length.

[0039] According to the third aspect of the invention, the gateinsulating film capacitance can be larger than that in a semiconductordevice having a gate insulating film formed of a silicon oxide film, sothat the driving capability of the semiconductor device can be enhanced.

[0040] According to the fourth aspect of the invention, the thirdinsulating film is not formed on the upper surface of the firstinsulating film. Accordingly, when source/drain wiring is formed in thefirst insulating film to make electrical contact with the source/drainregions, it is possible to avoid the trouble that the wiring capacitanceof the source/drain wiring increases due to the third insulating film.

[0041] According to the fifth aspect of the invention, it is possible toreduce the junction capacitance caused by the junction between thesource/drain regions and the impurity region.

[0042] According to the sixth aspect of the invention, it is possible toreduce the junction capacitance caused by the junction between thesource/drain regions and the impurity region. Furthermore, the oppositeconductivity types cancel each other in the part in which the impurityregion and the source/drain regions overlap. As a result, the depth ofthe source/drain regions becomes shallower under the sidewalls, thusfurther effectively suppressing the short-channel effect.

[0043] According to the seventh aspect of the invention, the gateelectrode is surrounded by the second and fourth insulating films madeof a different material from that of the first insulating film. Hence,the self-aligned contact formation technique can be used when forming acontact hole in the first insulating film.

[0044] According to the eighth aspect of the invention, the gate lengthin the upper part of the gate electrode can be still longer to furtherreduce the gate resistance.

[0045] According to the ninth aspect of the invention, reflecting theshape of the sidewalls, the gate length in the upper part of the gateelectrode is longer than that in its lower part. Hence the gateresistance can be reduced without enlarging the channel length under thegate insulating film.

[0046] According to the tenth aspect of the invention, in the step(d-1), only the second film can be removed without removing the firstinsulating film. In the step (d-2), only the first film can be removedwithout removing the sidewalls. Furthermore, the main surface of thesubstrate can be protected from damage when removing the first film.

[0047] According to the eleventh aspect of the invention, only thestructure can be removed without removing the first insulating film.Furthermore, the main surface of the substrate can be protected fromdamage when removing the structure.

[0048] According to the twelfth aspect of the invention, the gateinsulating film capacitance can be larger than that of a gate insulatingfilm formed of a silicon oxide film, so that the driving capability ofthe semiconductor device can be enhanced.

[0049] According to the thirteenth aspect of the invention, the thirdinsulating film formed on the upper surface of the first insulating filmin the step (x-1) is removed in the step (x-2). Accordingly, whensource/drain wiring for making electric contact with the source/drainregions is formed in the first insulating film, it is possible toprevent the wiring capacitance of the source/drain wiring fromincreasing due to the third insulating film.

[0050] According to the fourteenth aspect of the invention, the thirdinsulating film can be removed at the same time in the process ofthinning the conductor film for forming the gate electrode. Hence, thethird insulating film formed on the upper surface of the firstinsulating film can be removed without increasing the number ofmanufacturing process steps.

[0051] According to the fifteenth aspect of the invention, the processof thinning the conductor film is stopped when the third insulating filmis exposed, and the third insulating film formed on the upper surface ofthe first insulating film is removed by etching. Accordingly, the upperpart of the gate electrode having a longer gate length is not removed inthe thinning process, and therefore the gate resistance can be furtherreduced.

[0052] According to the sixteenth aspect of the invention, an impurityregion having an opposite conductivity type to that of the source/drainregions and for adjusting the operation threshold voltage of thesemiconductor device can be locally formed in the substrate only underthe gate insulating film. Hence junction capacitance caused by thejunction between the source/drain regions and the impurity region can bereduced.

[0053] According to the seventeenth aspect of the invention, an impurityregion having an opposite conductivity type to that of the source/drainregions and for adjusting the operation threshold voltage of thesemiconductor device can be locally formed in the substrate only underthe gate insulating film and the sidewalls. Hence junction capacitancecaused by the junction between the source/drain regions and the impurityregion can be reduced. Furthermore, the opposite conductivity typescancel each other in the part in which the impurity region and thesource/drain regions overlap. As a result, the depth of the source/drainregions under the sidewalls becomes shallower and the effect ofsuppressing the short-channel effect is enhanced.

[0054] According to the eighteenth aspect of the invention, the gateelectrode can be surrounded by the second and fourth insulating filmsformed of a different material from that of the first insulating film.Accordingly, the self-aligned contact formation technique can be usedwhen forming a contact hole in the first insulating film.

[0055] According to the nineteenth aspect of the invention, the gatelength in the upper part of the gate electrode can be still longer tofurther reduce the gate resistance.

[0056] The present invention has been made to solve the above-describedproblems, and an object of the present invention is to obtain asemiconductor device in which the channel length can be reduced withoutincreasing the gate resistance so that the driving capability of MOSFETcan be improved to realize higher-speed operation and a manufacturingmethod thereof, and to obtain a semiconductor device having a gateelectrode which allows the use of the self-aligned contact formationtechnique and its manufacturing method.

[0057] These and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0058]FIG. 1 is a sectional view showing the structure of an MOSFETaccording to a first preferred embodiment of the present invention.

[0059] FIGS. 2 to 14 are sectional views showing a method ofmanufacturing the MOSFET of the first preferred embodiment of theinvention in the order of processes.

[0060] FIGS. 15 to 18 are sectional views showing other methods ofmanufacturing the MOSFET of the first preferred embodiment of theinvention in the order of processes.

[0061]FIG. 19 is a sectional view showing the structure of an MOSFETaccording to a second preferred embodiment of the present invention.

[0062] FIGS. 20 to 22 are sectional views showing a method ofmanufacturing the MOSFET of the second preferred embodiment of theinvention in the order of processes.

[0063]FIGS. 23 and 24 are sectional views showing another method ofmanufacturing the MOSFET of the second preferred embodiment of theinvention in the order of processes.

[0064]FIG. 25 is a sectional view showing the structure of an MOSFETaccording to a third preferred embodiment of the present invention.

[0065]FIGS. 26 and 27 are sectional views showing a method ofmanufacturing the MOSFET of the third preferred embodiment of theinvention in the order of processes.

[0066]FIG. 28 is a sectional view showing the structure of an MOSFETaccording to a fourth preferred embodiment of the present invention.

[0067]FIG. 29 is a sectional view showing a process step in a method ofmanufacturing the MOSFET of the fourth preferred embodiment of theinvention.

[0068]FIG. 30 is a sectional view showing the structure of an MOSFETaccording to a fifth preferred embodiment of the present invention.

[0069]FIGS. 31 and 32 are sectional views showing a method ofmanufacturing the MOSFET of the fifth preferred embodiment of theinvention.

[0070]FIG. 33 is a sectional view showing the structure of an MOSFETaccording to a sixth preferred embodiment of the invention.

[0071]FIGS. 34 and 35 are sectional views showing a method ofmanufacturing the MOSFET of the sixth preferred embodiment of theinvention in the order of processes.

[0072]FIG. 36 is a sectional view showing a structure of a conventionalMOSFET.

[0073] FIGS. 37 to 42 are sectional views showing a method ofmanufacturing the conventional MOSFET in the order of processes.

[0074]FIG. 43 is a sectional view showing another structure of aconventional MOSFET.

[0075] FIGS. 44 to 50 are sectional views showing another method formanufacturing the conventional MOSFET in the order of processes.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0076] First Preferred Embodiment

[0077]FIG. 1 is a sectional view showing the structure of an MOSFETaccording to a first preferred embodiment of the present invention. Asshown in FIG. 1, the MOSFET of the first preferred embodiment has asemiconductor substrate 1, a trench-type element isolation structure 2formed in the element isolation region in the main surface of thesemiconductor substrate 1, a pair of extensions 3 and source/drainregions 4 selectively formed in the element formation region in the mainsurface of the semiconductor substrate 1 to face each other through achannel region 50, a silicon oxide film 5 formed on the trench-typeelement isolation structure 2 and on the source/drain regions 4 with asilicon oxide film 12 interposed therebetween, sidewalls 6 formed on thesides of the silicon oxide film 5, a gate insulating film 7 formed onthe main surface of the semiconductor substrate 1 in the part in whichthe channel region 50 is formed, and a gate electrode 8 formed to fillthe recessed portion formed by the sides of the sidewalls 6 and theupper surface of the gate insulating film 7.

[0078] FIGS. 2 to 14 are sectional views showing a method formanufacturing the MOSFET of the first preferred embodiment of theinvention in the order of process steps. First, the trench-type elementisolation structure 2 filled with insulating film is formed in theelement isolation region in the main surface of the semiconductorsubstrate 1 made of single crystal silicon. Subsequently, to form a welland to adjust the operation threshold voltage of the MOSFET, boron ions9 are implanted into the semiconductor substrate 1 by an ionimplantation (FIG. 2).

[0079] Next, a silicon oxide film 10 having a film thickness of about 3to 10 nm is formed by a thermal oxidation on the main surface of thesemiconductor substrate 1. Subsequently, a polysilicon film 11 having afilm thickness of about 200 nm is formed by CVD on the silicon oxidefilm 10 (FIG. 3). Next, the polysilicon film 11 is patterned into givenshape by photolithography and anisotropic dry etching to selectivelyform a dummy electrode 13 (a structure) composed of the polysilicon filmon the silicon oxide film 10 (FIG. 4).

[0080] Next, arsenic ions 15 are implanted into the semiconductorsubstrate 1 by an ion implantation, with an implant energy in the rangeof 5 to 30 keV and in the implant direction inclined at 30 to 70 degreeswith respect to the normal direction of the main surface of thesemiconductor substrate 1. This forms the extensions 3 in the mainsurface of the semiconductor substrate 1 (FIG. 5). Next, arsenic ions 16are implanted into the semiconductor substrate 1 by an ion implantation,with an implant energy in the range of 10 to 50 keV and in the implantdirection perpendicular to or inclined at about 10 degrees with respectto the normal direction of the main surface of the semiconductorsubstrate 1. This forms the source/drain regions 4 in the main surfaceof the semiconductor substrate 1; the source/drain regions are deeperthan the extensions 3 and extend in less distance under the dummyelectrode 13 (FIG. 6). Then the implanted arsenic ions 16 are activatedby a thermal treatment.

[0081] Next, a silicon oxide film having a film thickness of about 400nm is formed by a CVD over the entire surface. An insulating film madeof a material having a smaller dielectric constant than the siliconoxide film may be formed in place of the silicon oxide film.Subsequently, the silicon oxide film is polished by a CMP method untilthe upper surface of the dummy electrode 13 is exposed to form thesilicon oxide film 5 (FIG. 7). Next the dummy electrode 13 is removed bya dry etching or wet etching (FIG. 8). In FIG. 8, the silicon oxide film5 serves as a mold for forming the gate electrode.

[0082] Next, a silicon nitride film 17 having a film thickness of about10 to 50 nm is formed by a CVD over the entire surface (FIG. 9). Next,the silicon nitride film 17 is etched by an anisotropic dry etchingwhose etching rate is higher in the direction of the depth of thesemiconductor substrate 1, so as to form the sidewalls 6 made of thesilicon nitride film on the sides of the silicon oxide film 5 (FIG. 10).Next, the silicon oxide film 10 is removed by a wet etching using HF inthe part in which the silicon oxide film 5 and the sidewalls 6 are notformed to expose the main surface of the semiconductor substrate 1. Atthis time, the silicon oxide film 12 remains on the main surface of thesemiconductor substrate 1 as the unremoved part of the silicon oxidefilm 10 (FIG. 11).

[0083] Next, the gate insulating film 7 made of silicon oxide filmhaving a film thickness of about 2 to 10 nm is formed by a thermaloxidation on the main surface of the semiconductor substrate 1. As aresult, the sides of the sidewalls 6 and the upper surface of the gateinsulating film 7 form a recessed portion 18 (FIG. 12). As shown in FIG.12, reflecting the shape of the sidewalls 6, the recessed portion 18 isin inversely tapered form which spreads toward the top. Next, a tungstennitride film 19 having a film thickness of about 20 to 100 nm is formedover the entire surface by a CVD or sputtering. Subsequently, a tungstenfilm 20 having a film thickness of about 100 to 400 nm is formed overthe entire surface by a CVD or sputtering (FIG. 13). The tungstennitride film 19 serves as barrier metal for inhibiting reaction betweenthe gate insulating film 7 and the tungsten film 20.

[0084] Next, the tungsten film 20 and the tungsten nitride film 19 arepolished away (thinned) by CMP until the upper surface of the siliconoxide film 5 is exposed. Thus the gate electrode 8 is formed with thetungsten nitride film 21 and the tungsten film 22 to fill the recessedportion 18 (FIG. 14). The structure shown in FIG. 1 is obtained throughthese processes.

[0085] While a method of manufacturing NMOSFET has been described above,PMOSFET can be manufactured by using an ion-implanted dopant of theopposite conductivity type. Further, CMOSFET can be manufactured byperforming selective ion implantation using photolithography techniqueto form NMOSFET and PMOSFET.

[0086] Although the gate insulating film 7 is newly formed after removalof the silicon oxide film 10 in the example above, the silicon oxidefilm 10 may be used as a gate insulating film without removal. Further,while the gate insulating film 7 made of silicon oxide film is formed bythermal oxidation in the example above, a gate insulating film made ofnitrided oxide may be formed by adding gas, such as NO, N₂O, NH₃, in thethermal oxidation. Moreover, while the tungsten nitride film 19 is usedas a barrier metal in the example above, a film of other metal nitride,such as titanium nitride film or tantalum nitride film, may be used inplace of the tungsten nitride film. In the example above, the tungstenfilm 22 is used as a metal film for the gate electrode 8, but othermetal film, such as aluminum film, may be used in place of the tungstenfilm.

[0087] As has been described above, according to the MOSFET of the firstpreferred embodiment and its manufacturing method, the gate electrode 8is formed after the sidewalls 6 are formed on the sides of the siliconoxide film 5. Accordingly, reflecting the shape of the sidewalls 6, thegate electrode 8 can be formed in an inversely tapered shape with itsgate length in the upper part being longer than the gate length in thelower part. As a result, the channel length can be reduced withoutincreasing the gate resistance, and the driving capability of the MOSFETcan be increased to increase the operating speed. Furthermore, since thechannel length is shorter than the gate length of the dummy electrode 13by the width of the sidewalls 6, the channel length can be shorter thanthe gate length defined by the minimum resolution limit in thephotolithography technique adopted when forming the dummy electrode 13.

[0088] The sidewalls 6 are composed of silicon nitride film.Accordingly, when removing the silicon oxide film 10 by using HF afterformation of the sidewalls 6, and when cleaning the main surface of thesemiconductor substrate 1 with HF before formation of the gateinsulating film 7, the sidewalls 6 are not removed together andtherefore the channel length is not lengthened.

[0089] The dummy electrode 13 is formed on the silicon oxide film 10.Accordingly, even when the dummy electrode 13 is removed by dry etching,the presence of the silicon oxide film 10 prevents the main surface ofthe semiconductor substrate 1 from being damaged. Similarly, thesidewalls 6 are formed on the silicon oxide film 10, too. Hence, whenetching the silicon nitride film 17 to form the sidewalls 6, it can beetched by using anisotropic dry etching with a high etching selectivitybetween silicon nitride film, the material of the sidewalls 6, andsilicon oxide film so that the main surface of the semiconductorsubstrate 1 will not be damaged. As a result, the interface state information of the gate insulating film 7 on the main surface of thesemiconductor substrate 1 can be reduced to enhance the reliability ofthe gate insulating film 7.

[0090] FIGS. 15 to 18 are sectional views showing, in the order ofprocesses, other methods for manufacturing the MOSFET of the firstpreferred embodiment of the present invention. Instead of forming thesilicon oxide film 10 and the polysilicon film 11 in the process of FIG.3, a silicon nitride film 23 is formed as shown in FIG. 15. Then thedummy electrode can be formed with the silicon nitride film 23. Then,instead of removing the dummy electrode 13 in the process of FIG. 8 andremoving the silicon oxide film 10 in the process of FIG. 11, the dummyelectrode made of silicon nitride film 23 is removed by a wet etchingusing phosphoric acid as shown in FIG. 16. This manufacturing method,too, is capable of preventing the main surface of the semiconductorsubstrate 1 from being damaged when removing the dummy electrode, thusenhancing the reliability of the gate insulating film 7.

[0091] For another method, instead of forming the silicon oxide film 10and the polysilicon film 11 in the process shown in FIG. 3, the siliconoxide film 10 and a silicon nitride film 24 are formed in this order asshown in FIG. 17. Thus the dummy electrode can be formed with thesilicon nitride film 24 on the silicon oxide film 10. Then, instead ofremoving the dummy electrode 13 in the process shown in FIG. 8, thedummy electrode made of silicon nitride film 24 is removed, as shown inFIG. 18, by a wet etching using phosphoric acid or by an anisotropic dryetching with a high etching selectivity between silicon nitride film andsilicon oxide film. This manufacturing method, too, is capable ofpreventing the main surface of the semiconductor substrate 1 from beingdamaged when the dummy electrode is removed and when the sidewalls 6 areformed, leading to higher reliability of the gate insulating film 7.

[0092] Second Preferred Embodiment

[0093]FIG. 19 is a sectional view showing the structure of an MOSFETaccording to a second preferred embodiment of the present invention. Asshown in FIG. 19, on the basis of the MOSFET of the first preferredembodiment shown in FIG. 1, the MOSFET of the second preferredembodiment has a gate insulating film 25 made of a material having alarger dielectric constant than silicon oxide film, in place of the gateinsulating film 7 made of silicon oxide film.

[0094] FIGS. 20 to 22 are sectional views showing a method ofmanufacturing the MOSFET of the second preferred embodiment of theinvention in the order of processes. First, the same structure as thatshown in FIG. 11 is obtained through the same processes as those in theabove-described first preferred embodiment. Next, a tantalum oxide film26 having a film thickness of about 5 to 30 nm is formed by CVD orsputtering on the entire surface (FIG. 20). Next, as in the firstpreferred embodiment, the tungsten nitride film 19 and the tungsten film20 are formed over the entire surface in this order (FIG. 21).

[0095] Next, the tungsten film 20, tungsten nitride film 19, andtantalum oxide film 26 are polished by CMP until the upper surface ofthe silicon oxide film 5 is exposed, thus forming the gate electrode 8made of the tungsten nitride film 21 and the tungsten film 22 and thegate insulating film 25 made of the tantalum oxide film (FIG. 22). Thestructure shown in FIG. 19 is obtained through these processes.

[0096] While a tantalum oxide film is used as the gate insulating filmmade of a material having a larger dielectric constant than the siliconoxide film in the example above, other high-dielectric-constant film,such as BST or PZT film, can be used in place of the tantalum oxidefilm.

[0097] As described above, according to the MOSFET of the secondpreferred embodiment and its manufacturing method, the gate insulatingfilm 25 is formed by using a material having a larger dielectricconstant than the silicon oxide film. Hence, as compared with the MOSFEThaving the gate insulating film 7 made of silicon oxide film in thefirst preferred embodiment, the gate insulating film capacitance can bemade larger if the film thickness of the gate insulating film 7 and thefilm thickness of the gate insulating film 25 are the same, leading tohigher driving capability of the MOSFET.

[0098] The tantalum oxide film 26 formed on the silicon oxide film 5 isremoved. This prevents the problem that the wiring capacitance of thesource/drain wiring formed later increases to slow down the operationspeed of the circuit.

[0099]FIGS. 23 and 24 are sectional views showing, in the order ofprocesses, another method for manufacturing the MOSFET of the secondpreferred embodiment of the invention. First, the same structure as thatshown in FIG. 21 is obtained through the same processes as thosedescribed above. Next, the tungsten film 20 and the tungsten nitridefilm 19 are polished away by CMP until the upper surface of the tantalumoxide film 26 is exposed (FIG. 23). Next, the tantalum oxide film 26exposed by polishing is removed by a dry etching (FIG. 24). When theMOSFET is manufactured by this method, the upper part of the gateelectrode 8 having a longer gate length is not removed by polishing.Accordingly, this method provides the effect of further reducing thegate resistance, in addition to the same effects described above. On theother hand, when the tantalum oxide film 26 is removed together bypolishing when forming the gate electrode 8 as shown in FIG. 22, themanufacturing process can be simplified since the dry etching processshown in FIG. 24 is not required.

[0100] Third Preferred Embodiment

[0101]FIG. 25 is a sectional view showing the structure of an MOSFETaccording to a third preferred embodiment of the invention. As shown inFIG. 25, on the basis of the MOSFET of the first preferred embodimentshown in FIG. 1, the MOSFET of the third preferred embodiment has achannel doping region 28 for adjusting the operation threshold voltageof the MOSFET, which is locally formed in the semiconductor substrate 1under the gate insulating film 7.

[0102]FIGS. 26 and 27 are sectional views showing, in the order ofprocesses, a method of manufacturing the MOSFET according to the thirdpreferred embodiment of the invention. First, the trench-type elementisolation structure 2 filled with insulating film is formed in theelement isolation region in the main surface of the semiconductorsubstrate. 1 made of single crystal silicon. Subsequently, to form awell, boron ions 29 are implanted into the semiconductor substrate 1 byan ion implantation (FIG. 26). At this time, unlike the first preferredembodiment, ion implantation for adjusting the operation thresholdvoltage of the MBSFET is not performed. After that, the same structureas that shown in FIG. 10 is obtained through the same processes as thosein the first preferred embodiment.

[0103] Next, boron ions 30 are implanted into the semiconductorsubstrate 1 by using the silicon oxide film 5 and the sidewalls 6 asmasks, with an implant energy of about 50 keV and a concentration ofabout 1×10¹² to 3×10¹³/cm². This locally forms the channel doping region28 in the semiconductor substrate 1 (FIG. 27). Then the structure shownin FIG. 25 is obtained through the same processes as those in the firstpreferred embodiment.

[0104] In this way, according to the MOSFET of the third preferredembodiment and its manufacturing method, the channel doping region 28 islocally formed in the semiconductor substrate 1 under the gateinsulating film 7. Hence the junction capacitance formed by the channeldoping region 28 having a first conductivity type (p type in theexample) and the extensions 3 and the source/drain regions 4 having asecond conductivity type (n type in the example) can be reduced, so asto speed up the operation of the MOSFET.

[0105] Further, since the channel doping region 28 is subjected to aless number of thermal treatments, it is possible to prevent the boronions 30 implanted into the semiconductor substrate 1 from beingthermally diffused more than necessary. This enables adequate control ofthe operation threshold voltage of the MOSFET.

[0106] Fourth Preferred Embodiment

[0107]FIG. 28 is a sectional view showing the structure of an MOSFETaccording to a fourth preferred embodiment of the present invention. Asshown in FIG. 28, on the basis of the MOSFET of the first preferredembodiment shown in FIG. 1, the MOSFET of the fourth preferredembodiment has a channel doping region 31 for adjusting the operationthreshold voltage of the MOSFET, which is locally formed in thesemiconductor substrate 1 under the gate insulating film 7 and thesidewalls 6.

[0108]FIG. 29 is a sectional view showing a process in a method ofmanufacturing the MOSFET of the fourth preferred embodiment of theinvention. First, as shown in FIG. 26, the trench-type element isolationstructure 2 is formed in the main surface of the semiconductor substrate1 and then boron ions 29 are implanted into the semiconductor substrate1 to form a well. At this time, as in the third preferred embodiment,ion implantation is not performed for the purpose of adjusting theoperation threshold voltage of the MOSFET. Subsequently, the samestructure as that shown in FIG. 8 is obtained through the same processesas those in the first preferred embodiment.

[0109] Next, boron ions 32 are implanted into the semiconductorsubstrate 1 by an ion implantation using the silicon oxide film 5 as amask, with an implant energy of about 50 keV and a concentration ofabout 1×10¹² to 3×10³/cm². This locally forms the channel doping region31 in the semiconductor substrate 1 (FIG. 29). After this, the structureshown in FIG. 28 is obtained through the same processes as those in thefirst preferred embodiment.

[0110] In this way, according to the MOSFET of the fourth preferredembodiment and its manufacturing method, the channel doping region 31 islocally formed in the semiconductor substrate 1 under the gateinsulating film 7 and the sidewalls 6. Accordingly, similarly to theMOSFET of the third preferred embodiment, the operation speed of theMOSFET can be enhanced.

[0111] Further, in the part in which the upper part of the channeldoping region 31 of a first conductivity type and the lower part of theextensions 3 of a second conductivity type overlap, the oppositeconductivity types cancel out. As a result, the depth of the extensions3 from the main surface of the semiconductor substrate 1 becomesshallower, which more effectively suppresses the short-channel effect ofthe MOSFET.

[0112] Fifth Preferred Embodiment

[0113]FIG. 30 is a sectional view showing the structure of an MOSFETaccording to a fifth preferred embodiment of the present invention. Asshown in FIG. 30, in the MOSFET of the fifth preferred embodiment, onthe basis of the MOSFET of the first preferred embodiment shown in FIG.1, a gate electrode 33 is formed in place of the gate electrode 8, withits upper surface located lower than the upper surface of the siliconoxide film 5, and a silicon nitride film 34 is formed on the uppersurface of the gate electrode 33 to surround the gate electrode 33 withthe sidewalls 6.

[0114]FIGS. 31 and 32 are sectional views showing, in the order ofprocess steps, a method of manufacturing the MOSFET of the fifthpreferred embodiment of the invention. First, the same structure as thatshown in FIG. 14 is obtained through the same processes as those in thefirst preferred embodiment. Next, part of the upper portion of the gateelectrode 8 is removed to form the gate electrode 33 (FIG. 31). Next, asilicon nitride film 35 having a film thickness of about 100 nm isformed by a CVD over the entire surface (FIG. 32). Next, the siliconnitride film 35 is polished away by CMP until the upper surface of thesilicon oxide film 5 is exposed, and the structure shown in FIG. 30 isthus obtained.

[0115] In this way, according to the MOSFET of the fifth preferredembodiment and its manufacturing method, the gate electrode 33 issurrounded by the sidewalls 6 made of silicon nitride film and thesilicon nitride film 34 formed on the upper surface of the gateelectrode 33. Accordingly, the self-aligned contact formation techniquecan be adopted when forming a contact hole in the silicon oxide film 5in a later process to make electric contact with the source/drainregions 4. That is to say, only the silicon oxide film can beselectively etched away by the use of a large etching selectivitybetween silicon oxide film and silicon nitride film, so that the contacthole and the gate electrode 33 can be prevented from coming in contactwith each other.

[0116] Although the silicon nitride film 35 is removed by a CMP in theexample above, the silicon nitride film 35 may be removed by ananisotropic etching. In this case, when the distance between theopposing parts of the silicon oxide film 5 is long relatively to thefilm thickness of the deposited silicon nitride film 35 (twice or more,for example), the silicon nitride film 35 is removed in the part overthe center of the gate electrode 33. However, also in this case, theself-aligned contact formation technique can be used since the siliconnitride film 35 remains on the peripheral part of the gate electrode 33.

[0117] Sixth Preferred Embodiment

[0118]FIG. 33 is a sectional view showing the structure of an MOSFETaccording to a sixth preferred embodiment of the present invention. Asshown in FIG. 33, on the basis of the MOSFET of the first preferredembodiment shown in FIG. 1, the MOSFET of the sixth preferred embodimenthas, in place of the gate electrode 8, a gate electrode 36 having itsperiphery extending on the upper surface of the silicon oxide film 5.

[0119]FIGS. 34 and 35 are sectional views showing a method ofmanufacturing the MOSFET of the sixth preferred embodiment of theinvention in the order of processes. First, the same structure as thatshown in FIG. 13 is obtained through the same processes as those in thefirst preferred embodiment. Next, a photoresist 37 having given patternis formed by a photolithography on the tungsten film 20 (FIG. 34). Asshown in FIG. 34, the side ends of the photoresist 37 extend over thesilicon oxide film 5. The amount of extension of the photoresist 37 overthe silicon oxide film 5 can be adjusted by varying the mask pattern ofthe photomask used to form the photoresist 37.

[0120] Next, the tungsten nitride film 19 and the tungsten film 20 areetched away by using an anisotropic dry etching in which the etchingrate is higher in the direction of the depth of the semiconductorsubstrate 1, and the gate electrode 36 can thus be made with thetungsten nitride film 38 and the tungsten film 39 (FIG. 35). Next, thephotoresist 37 on the tungsten nitride film 39 is removed to obtain thestructure shown in FIG. 33.

[0121] In this way, according to the MOSFET of the sixth preferredembodiment and its manufacturing method, the peripheral part of the gateelectrode 36 extends on the upper surface of the silicon oxide film 5.Accordingly, as compared with the MOSFETs of the first to fifthpreferred embodiments, the gate length in the upper part of the gateelectrode 36 can be further lengthened to further reduce the gateresistance.

[0122] Further, since CMP is not used when removing the tungsten nitridefilm 19 and the tungsten film 20 on the silicon oxide film 5, themanufacturing cost can be reduced. Furthermore, the silicon oxide film 5can be used as an etching stopper in the dry etching, so that theetching can be stopped relatively easily.

[0123] While the invention has been described in detail, the foregoingdescription is in all aspects illustrative and not restrictive. It isunderstood that numerous other modifications and variations can bedevised without departing from the scope of the invention.

What is claimed is:
 1. A semiconductor device, comprising: a substrate;source/drain regions formed in a main surface of said substrate with achannel region interposed therebetween; a gate insulating film formed onsaid main surface of said substrate in an area in which said channelregion is formed; and an inversely tapered gate electrode formed on anupper surface of said gate insulating film.
 2. A semiconductor device,comprising: a substrate; source/drain regions formed in a main surfaceof said substrate with a channel region interposed therebetween; a firstinsulating film formed on said main surface of said substrate in an areain which said source/drain regions are formed; sidewalls composed of asecond insulating film and formed on sides of said first insulatingfilm; a gate insulating film composed of a third insulating film andformed on said main surface of said substrate in an area in which saidchannel region is formed; and a gate electrode formed to fill aninversely tapered recessed portion formed by sides of said sidewalls andan upper surface of said gate insulating film.
 3. The semiconductordevice according to claim 2, wherein said third insulating film iscomposed of a material having a larger dielectric constant than siliconoxide film.
 4. The semiconductor device according to claim 3; whereinsaid third insulating film is one of a tantalum oxide film, a BST film,and a PZT film.
 5. The semiconductor device according to claim 3,wherein said third insulating film is formed to extend only onto saidsides of said sidewalls.
 6. The semiconductor device according to claim2, further comprising an impurity region locally formed in saidsubstrate only under said gate insulating film and having a conductivitytype which is opposite to that of said source/drain regions.
 7. Thesemiconductor device according to claim 2, wherein said source/drainregions are formed in said main surface of said substrate also in areasin which said sidewalls are formed, and said semiconductor devicefurther comprises an impurity region locally formed in said substrateonly under said gate insulating film and said sidewalls and having aconductivity type which is opposite to that of said source/drainregions.
 8. The semiconductor device according to claim 2, furthercomprising a fourth insulating film formed on an upper surface of saidgate electrode and surrounding said gate electrode with said sidewalls,wherein said second and fourth insulating films are composed of amaterial which is different from that of said first insulating film. 9.The semiconductor device according to claim 2, wherein said gateelectrode has its peripheral part formed to extend on an upper surfaceof said first insulating film.
 10. A method for manufacturing asemiconductor device, comprising the steps of: (a) forming a structureon a main surface of a substrate in an area in which a gate electrode isformed later; (b) forming source/drain regions in said main surface ofsaid substrate in an area in which said structure is not formed; (c)forming a first insulating film on said main surface of said substratein an area in which said structure is not formed; (d) after said step(c), removing said structure; (e) forming a second insulating film onthe construction obtained by said step (d) and etching said secondinsulating film by an anisotropic etching whose etching rate is higherin depth direction of said substrate to form sidewalls on sides of saidfirst insulating film; (f) forming a gate insulating film composed of athird insulating film on said main surface of said substrate in an areain which said first insulting film and said sidewalls are not formed;and (g) forming said gate electrode to fill an inversely taperedrecessed part formed by sides of said sidewalls and an upper surface ofsaid gate insulating film.
 11. The semiconductor device manufacturingmethod according to claim 10, wherein, in said step (a), said structureis formed by stacking a first film composed of a material which isdifferent from that of said second insulating film and a second filmcomposed of a material which is different from that of said firstinsulating film in this order, and said step (d) comprises the steps of;(d-1) between said step (c) and said step (e), removing said second filmwith said first film left unremoved, and (d-2) between said step (e) andsaid step (f), removing said first film by a wet etching.
 12. Thesemiconductor device manufacturing method according to claim 10,wherein, in said step (a), said structure is formed with a materialwhich is different from that of said first insulating film, and in saidstep (d), said structure is removed by a wet etching.
 13. Thesemiconductor device manufacturing method according to claim 10,wherein, in said step (f), said third insulating film is formed with amaterial having a larger dielectric constant than silicon oxide film.14. The semiconductor device manufacturing method according to claim 13,wherein said step (f) comprises the steps of; (x-1) forming said thirdinsulating film on the construction obtained by said step (e), and (x-2)removing said third insulating film formed on an upper surface of saidfirst insulating film.
 15. The semiconductor device manufacturing methodaccording to claim 14, wherein said step (g) comprises the steps of;(y-1) after said step (x-1), forming a conductor film which is amaterial of said gate electrode on said third insulating film, and (y-2)after said step (y-1), thinning said conductor film until said uppersurface of said first insulating film is exposed to form said gateelectrode, and wherein said step (x-2) is performed together in theprocess in which said step (y-2) is performed.
 16. The semiconductordevice manufacturing method according to claim 14, wherein said step (g)comprises the steps of; (z-1) after said step (x-1), forming a conductorfilm which is a material of said gate electrode on said third insulatingfilm, and (z-2) between said step (z-1) and said step (x-2), thinningsaid conductor film until said third insulating film formed on saidupper surface of said first insulating film is exposed to form said gateelectrode, and wherein, in said step (x-2), said third insulating filmis removed by etching said third insulating film exposed in said step(z-2).
 17. The semiconductor device manufacturing method according toclaim 10, further comprising the step of: (h) between said step (e) andsaid step (f), introducing an impurity into said substrate by using saidfirst insulating film and said sidewalls as masks to form an impurityregion having a conductivity type which is opposite to that of saidsource/drain regions.
 18. The semiconductor device manufacturing methodaccording to claim 10, wherein, in said step (b), said source/drainregions are formed to extend also under peripheral part of saidstructure in said main surface of said substrate, and said manufacturingmethod further comprises the step of: (i) between said step (d) and saidstep (e), introducing an impurity into said substrate by using saidfirst insulating film as a mask to form an impurity region having aconductivity type which is opposite to that of said source/drainregions.
 19. The semiconductor device manufacturing method according toclaim 10, wherein said first insulating film is composed of a materialwhich is different from that of said second insulating film, and saidmanufacturing method further comprises the steps of; (j) removing saidgate electrode for a given film thickness from its upper surface, and(k) after said step (j), forming a fourth insulating film composed of amaterial which is different from that of said first insulating film onsaid gate electrode.
 20. The semiconductor device manufacturing methodaccording to claim 10, wherein said step (g) comprises the steps of;(g-1) forming a conductor film which is a material of said gateelectrode on the construction obtained by said step (f), and (g-2)patterning said conductor film to form said gate electrode having itsperipheral part extending on an upper surface of said first insulatingfilm.